The present application relates to semiconductor device manufacturing, and more particularly to a method of reducing the overlay tolerance requirement for removing, i.e., cutting, unwanted semiconductor fins.
For more than three decades, the continued miniaturization of metal oxide semiconductor field effect transistors (MOSFETs) has driven the worldwide semiconductor industry. Various showstoppers to continued scaling have been predicated for decades, but a history of innovation has sustained Moore's Law in spite of many challenges. However, there are growing signs today that metal oxide semiconductor transistors are beginning to reach their traditional scaling limits. Since it has become increasingly difficult to improve MOSFETs and therefore complementary metal oxide semiconductor (CMOS) performance through continued scaling, further methods for improving performance in addition to scaling have become critical.
The use of non-planar semiconductor devices such as, for example, semiconductor fin field effect transistors (finFETs) is the next step in the evolution of complementary metal oxide semiconductor (CMOS) devices. Semiconductor fin field effect transistors (FETs) can achieve higher drive currents with increasingly smaller dimensions as compared to conventional planar FETs. In finFET devices, a functional gate structure straddles a semiconductor fin.
Semiconductor fins are formed by patterning a semiconductor substrate utilizing fin forming etch masks. Unwanted semiconductor fins can be removed by cutting some of the semiconductor fins after fin formation. As the semiconductor fin pitch shrinks, the requirement to cut the unwanted semiconductor fins becomes more problematic oftentimes leaving unwanted semiconductor fin residue or excessive semiconductor fin removal.
In view of the above, there is a continued need to provide a method for fabricating semiconductor fins in which unwanted semiconductor fins can be removed while avoiding the problems associated in the prior art.